WebMar 10, 2024 · csrr a0, mepc csrr a1, mtval csrr a2, mcause csrr a3, mhartid csrr a4, mstatus csrr a5, mscratch la t0, KERNEL_STACK_END ld sp, 0(t0) call m_trap In the … WebLKML Archive on lore.kernel.org help / color / mirror / Atom feed * [PATCH v6 0/3] Allow accessing CSR using CSR number @ 2024-04-25 8:38 Anup Patel 2024-04-25 8:38 ` [PATCH v6 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Anup Patel @ 2024-04-25 …
RISC-V MCU开发实战 (三):移植鸿蒙OS项目 - 知乎 - 知乎 …
WebNov 5, 2024 · This symbol comes from virt.lds la sp, _stack_end # Setting `mstatus` register: # 0b01 11: Machine's ... t6 csrr t6, mscratch save_gp 31, t5 # Restore the … http://osblog.stephenmarz.com/ch8.html how many days of school are there in michigan
The RISC-V Instruction Set Manual Volume II: Privileged
WebJun 14, 2024 · Hardware Floating Point. By Stephen Marz June 14, 2024. This is an article in the larger tutorial The Adventures of OS: Making a RISC-V Operating System using … Webmv a2, sp # arg 2: sp – pointer to all saved GPRs jal c_handler # call C function # return value is the PC to resume csrw mepc, a0 # restore mscratch and all GPRs addi s0, sp, 128; csrw mscratch, s0 lw x1, 4(sp); lw x3, 12(sp); ...; lw x31, 124(sp) lw x2, 8(sp) # restore sp at last eret # finish handling interrupt Webcsrrw sp, mscratch, sp: 1: #endif /* Save caller-saved registers on current thread stack. */ addi sp, sp, -__z_arch_esf_t_SIZEOF: 80000028: 7139 addi sp,sp,-64: DO_CALLER_SAVED(sr) ; 8000002a: c216 sw t0,4(sp) 8000002c: c41a sw t1,8(sp) 8000002e: c61e sw t2,12(sp) high speed router and modem